1. Field of the Invention
The present invention relates generally to the field of nonvolatile memory devices for use in computers and other devices. More particularly, the present invention relates to nonvolatile memory arrays that use magnetic tunnel junction memory elements as individual memory cells.
2. Description of the Related Art
Certain types of magnetic memory cells that use the magnetic state of a ferromagnetic region for altering the electrical resistance of materials located near the ferromagnetic region are collectively known as magnetoresistive (MR) memory cells. An array of magnetic memory cells is often called a magnetic random access memory (MRAM).
In comparison to metallic MR memory cells, which are based on giant magnetoresistance (GMR) or anisotropic magnetoresistance (AMR) devices, MRAM memory cells are based on magnetic tunnel junction (MTJ) devices and rely on substantially different physical principles. For example, GMR devices include at least two ferromagnetic layers that are separated by a thin metallic layer. In contrast, an MTJ device has two ferromagnetic layers that are separated by a thin insulating tunnel barrier. The magnetoresistance of an MTJ device results from a spin-polarized tunneling of conduction electrons between the two ferromagnetic layers that depends on the relative orientation of the magnetic moments of the two ferromagnetic layers.
FIG. 1A shows a portion of a conventional MRAM array that uses conventional magnetoresistive memory cells, such as disclosed by U.S. Pat. No. 5,640,343 to Gallagher et al. (the Gallagher xe2x80x2343 patent). The MRAM array shown in FIG. 1A includes a set of electrically conductive traces 1-3 in a horizontal plane that function as parallel word lines and a set of electrically conductive traces 4-9 in another horizontal plane that function as parallel bit lines. The word lines are oriented in a different direction from the bit lines, preferably at a right angle, so that the two sets of lines intersect when viewed from above. The MRAM array of FIG. 1A is referred to as a cross point array because memory cells are placed at the intersection point of crossing lines. The CAM array of FIG. 1A is formed on a substrate (not shown), such as a silicon, on which there would be other circuitry (also not shown). For clarity, a layer of insulative material that is located between the bit lines and word lines within the MRAM other than the intersecting regions is not shown. While three word lines and six bit lines are illustrated in FIG. 1A, the total number of lines is typically much larger.
A conventional memory cell 10 is located at each crossing point of the word lines and bit lines within an intersection region that is vertically spaced between the respective sets of lines. FIG. 1B shows an enlarged view of a conventional magnetoresistive memory cell 10. Memory cell 10 includes a vertical stack of a diode-like selection device 11, e.g., a silicon junction diode, connected electrically in series with a magnetic tunnel junction (MTJ) device 12. Memory cell 10 can be fabricated very densely because the cell has only two terminals and has a vertical current path through selection device 11 and MTJ 12.
Selection device 11 is a silicon junction diode that is formed from an n-type silicon layer 13 and a p-type silicon layer 14. The n-type silicon layer 13 is formed on and connected to word line 3. The p-type silicon layer 14 is connected to the MTJ 12 via a tungsten stud 15. MTJ 12 is formed from a series of layers of material that are stacked one on top of the other. MTJ 12 includes a template layer 16, such as Pt, an initial ferromagnetic layer 17, such as permalloy (Nixe2x80x94Fe), an antiferromagnetic layer (AF) 18, such as Mnxe2x80x94Fe, a fixed ferromagnetic layer (FMF) 19, such as Coxe2x80x94Fe or permalloy, a thin tunneling barrier layer 20 of alumina (Al2O3), a soft ferromagnetic layer (FMS) 21, such as a sandwich of thin Coxe2x80x94Fe with permalloy, and a contact layer 22, such as Pt. Additional details regarding conventional memory cell 10 are provided in U.S. Pat. No. 5,640,343 to Gallagher et al., which is incorporated by reference herein.
Diode 11 is necessary for preventing currents from flowing through alternate current paths, referred to herein as sneak currents. For instance, if in FIG. 1A, word line 2 is grounded and a bias of VA is applied to bit line 7, a signal current will flow through the selected cell (in this case the cell connecting word line 2 and bit line 7, referred to herein as cell 2,7). A very small current will flow through alternate paths, for example, via cells 2,6, 3,6 and 3,7 because the diode in cell 3,6 is reverse biased. The reverse currents for all of the unselected diodes in the memory matrix contribute to the total sneak current. In order to maintain the signal current to be of the same order of magnitude as the total sneak current for an nxc3x97n matrix, the rectification ratio of the selected diode must be greater than n2. Such a requirement for a diode requires a device-quality semiconducting diode material, which cannot easily be grown on top of a metallic word line, and implies that the diode will have a high resistance.
Additionally, the resistance of the diode, and more particularly the differential resistance of the diode, should be less than the resistance of the MTJ device so that sensing circuitry can easily detect changes in resistance of the MTJ device that represent the different states of the MTJ device. Thus, a large diode resistance implies a correspondingly large MTJ resistance so that MTJ device resistance changes can be easily detected. A high overall diode and MTJ resistance results in slow performance caused by RC delays, in addition to limited power levels during a sensing operation. Thus, a drawback associated with the Gallagher xe2x80x2343 memory cell is the high resistance of the diode between the two metal layers.
U.S. Pat. No. 5,734,605 to Zhu et al. discloses an alternative conventional MRAM cell that uses a transistor as a selection element for a memory cell. The Zhu et al. MRAM cell uses more space than a cross point cell because the cell has more than two terminals. Moreover, the cell must have a connection from the MTJ to the silicon surface where the transistor is located. The transistor also occupies more area than the tunnel junction occupies.
A very small, 2xc3x972 MTJ element array is disclosed by Z. G. Wang et al. in Spin Tunneling Random Access Memory, IEEE Transactions on Magnetics, Vol. 32 No. 5, 1996, pp. 4022-4024. Although individual cells in the disclosed 2xc3x972 array can be read without diodes, the non-linearity in these standard Al2O3 MTJs is insufficient for permitting selection in arrays that are larger than 2xc3x972 without significantly increasing the time to read a memory cell. Moreover, arrays having a 2xc3x972-array size are too small to be of technological use because the support circuitry would form too large an area on a chip, thereby making the storage density much too small.
To overcome the very small overall MRAM array size of Wang et al., U.S. patent application Ser. No. (Atty Docket No. AM9-99-0112) to Monsma et al. discloses an MTJ cell that uses a tunneling device having a non-linear current dependence through the device as a function of bias voltage. According to Monsma et al., amorphous or polycrystalline barriers are used for forming a non-linear tunnel selection device, such as a metal-barrier-metal (MBM) device, that is fabricated in series with the MTJ to form an MBM-MTJ memory cell. The voltage drop across an unselected MBM is Vmbm,u=0.5VA, with VA being the applied bias voltage used for selecting a cell. The voltage drop across a selected MBM is Vmbm,s=VAxe2x88x92Vmtj, with Vmtj being the voltage drop across the selected MTJ (about 0.2 V). Consequently, the difference in voltage drop across a selected MBM and an unselected MBM is 0.5VAxe2x88x92Vmtj, and not 0.5VA. Moreover, when a current through the MTJ device is used for writing or for assisting in writing the MTJ device, device selection is limited by a relatively large voltage drop across the MTJ device, thereby resulting in a total current that is more than twice the write current through a single cell. Additionally, the large voltage drop across the MTJ device results in an excessive power consumption.
What is needed is an MTJ memory cell having sufficient non-linearity for both reading and writing, in addition to having a lower and thicker barrier.
The present invention provides an MTJ memory cell having sufficient non-linearity for both reading and writing, in addition to having a lower and thicker barrier. The advantages of the present invention are provided by a non-linear magnetic tunnel junction storage element having a first ferromagnetic layer, a barrier layer, and a second ferromagnetic layer. According to the invention, the non-linear magnetic tunnel junction storage element has a non-linearity that is defined by a current having a first magnitude flowing through the non-linear magnetic tunnel junction storage element for a bias across the non-linear magnetic tunnel junction storage element of about 0.5 VA that is ten times or more smaller than a current having a second magnitude flowing through the non-linear magnetic tunnel storage element for a bias across the non-linear magnetic tunnel storage element of about 1 VA, where VA is an operating voltage of the non-linear magnetic tunnel junction storage element. Preferably, the operating voltage VA is about 1.0 Volts. The barrier layer of the non-linear magnetic tunnel storage element is one of an insulating or a semiconducting layer. When the barrier layer is an insulating layer, the insulating barrier layer in combination with the first and second ferromagnetic layers, has a barrier height that is less than about 1 eV. The non-metallic insulating layer can be formed from aluminum arsenide. When the barrier layer is formed from a semiconducting layer, the semiconducting material layer, in combination with the first and second ferromagnetic layers, has a barrier height that is less than about 1 eV. The semiconducting material layer can be formed from silicon, germanium or an oxidic semiconductor, such as titanium dioxide or zinc oxide.
The present invention also provides a non-volatile memory array having a substrate, a first plurality of electrically conductive traces formed on the substrate, a second plurality of electrically conductive traces formed on the substrate and overlapping first plurality of traces at a plurality of intersection regions, and a plurality of memory cells. Each memory cell is located at an intersection region between one of the first plurality of traces and one of the second plurality of traces. At least one memory cell includes a non-linear magnetic tunnel junction storage element. The non-linear magnetic tunnel junction storage element has at least a first ferromagnetic layer, a barrier layer and a second ferromagnetic layer. According to the invention, the non-linear magnetic tunnel junction storage element has a non-linearity that is defined by a current having a first magnitude flowing through the non-linear magnetic tunnel storage element for a bias across the non-linear magnetic tunnel storage element of about 0.5 VA that is ten times or more smaller than a current having a second magnitude flowing through the non-linear magnetic tunnel storage element for a bias across the non-linear magnetic tunnel storage element of about 1 VA, wherein VA is an operating voltage for a memory cell.